Cortex-M3 cores are thumb only i.e. they cannot execute ARM instructions. That said, there is a single xPSR3 register, which shows up as PSR register in gdb – wherein bit 24 is defined as the Thumb (T) bit. Executing code when T bit is not set leads to fault or lockup on Cortex-M3. PSR is set to 0x61000000 which confirms that the T bit is indeed set for us and we are in thumb mode.

Another way to realize that we are in thumb mode is by watching bit 0 of lr when function calls are made. And even though this is thumb only platform bl and blx instructions continue to set bit 0 of lr when the ARM core is running in thumb mode.

In my last post, when experimenting with the Raspbian toolchain, it was pretty clear that thumb instructions could not be generated from the toolchain. Thumb instructions were needed so we could compare apples to apples since the iPhone was using 16-bit thumb instructions. As a workaround, we made LLVM emit ARM instructions. It is a bit funny that in the end, our experiments were on thumb-only LPCxpresso. Looking at it another way, we started with 16-bit thumb instructions on iPhone, switched to 32-bit ARM instructions on Raspberry Pi, followed by Thumb-2 stuff on LPCxpresso.

ARM is a set of processor specifications that allows ARM licensees to make their own choices in their processor or platform design. Any generic statement about how something works in an ARM processor must therefore be carefully qualified because there are quite a few variations in terms of processor specifications, processors, and software (OS/toolchain).

I hope you enjoyed this series on ARM calling convention across a few platforms, as much as I did writing them.

1Please refer to my earlier posts for the C version of the square function.

2In fact the .w suffix forces the assembler to use 32-bit encoding for the instruction

3xPSR is a single 32-bit register that combines non-overlapping bits of 3 other PSRs, the APSR (Application Program Status Register), the IPSR (Interrupt Program Status Register) and the EPSR (Execution Program Status Register). The T bit is defined in the EPSR.

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